The electronics industry's aggressive shrinking of chip features below 50 nanometers and moving toward three-dimensional integrated circuits have made a dramatic impact on chip design and test. Contemporary system-on-chip (SoC) and system-in-package (SiP) designs embed more than a billion transistors running at operating frequencies in the gigahertz range. These designs can include a variety of digital, analog, mixed-signal, memory, optical, micro-electromechanical and radiofrequency circuits. The popularity of SoC circuits has led to an unprecedented increase in the test cost. This cost increase is primarily attributed to the difficulty in accessing embedded cores during testing, long test development and test application time, and large volumes of test data involved. Although network-on-chip (NoC) systems can alleviate some of the core communication problems, these structures in turn have further complicated the SoC test procedures.
On-chip test compression has established itself as one of the mainstream DFT (Design-for-testability) methodologies. By using on-chip test decompression and compression hardware, a tester can deliver test patterns in a compressed form, and the on-chip decompression hardware can expand (or decompress) the compressed test patterns into the actual test data to be loaded into scan chains. The latter operation is possible because only a small number of bits in the decompressed test patterns typically are specified bits designed to target one or more specific faults in the integrated circuit. The remaining unspecified bits of the decompressed test pattern are termed “don't care” bits and are typically randomly determined as a result of the decompressor structure. A test pattern with defined values for only specified bits is often referred to as a test cube. After the actual test data has been applied, the test response data are captured by the scan chains and are then compressed by the on-chip compression hardware (sometimes referred to as compactor). The compressed test response data are subsequently delivered back to the tester for analysis.
The application of compression techniques in SoC designs requires additional on-chip hardware infrastructure, including a test access mechanism (TAM) and test wrappers. Originally, TAMs were used to transport test stimuli from the SoC pins (circuit input channels) to the embedded cores and test responses from the embedded cores to the SoC pins (circuit output channels), while test wrappers formed the interface between the core and the SoC environment. In addition to dedicated TAMs, cost-effective SoC testing typically requires some form of test scheduling. Test scheduling for SoCs usually involves multiple test resources and cores with multiple tests. Unfortunately, even relatively simple test scheduling algorithms typically are NP (nondeterministic polynomial time)-complete problems. This is because test scheduling has been commonly formulated as a combinatorial open shop scheduling problem with a certain number of processors or as two or three-dimensional bin packing. These methods divide given channels into disjoint subsets. Each subset represents a test bus or a processor in the multiprocessor scheduling problem formulation. Different buses have different widths. Testing of cores can then be performed by accessing each core through only one of the test buses. Dedicated routing paths can be used to deliver tests to cores, while the test-scheduling problem is solved by means of integer linear programming.
Performing both TAM optimization and test scheduling can significantly affect the test time, test data volume, and test cost. U.S. Provisional Patent Application No. 61/314,569, entitled “SOC Testing In Test Compression Environment,” filed on Mar. 16, 2010 and International Patent Application No. PCT/US2011/028741, entitled “Test Scheduling And Test Access In Test Compression Environment,” filed on Mar. 16, 2011, which applications (referred to as the '569 application and the '028741 application, respectively, hereinafter) are incorporated herein by reference, disclose TAM optimization and test scheduling methods that can dynamically allocate a circuit's test resources. Dynamic channel allocation enables optimal usage of communication channels connecting individual decompressors with external test equipment. These methods, however, are test-pattern-dependent solutions. In particular, an optimal structure for TAM interconnection networks may be obtained only after test patterns are known or derived by running ATPG (automatic test pattern generation) and compression procedures. This dependency may make a design flow complicated.